formal design description

英 [ˈfɔːml dɪˈzaɪn dɪˈskrɪpʃn]

美 [ˈfɔːrml dɪˈzaɪn dɪˈskrɪpʃn]

【计】形式设计描述

双语例句

Formal verification can drastically reduce design time and cover completely, it uses hardware description, rather than stimuli or wave-forms, this can verify designs and detect error quickly.
形式化验证能大大减小设计时间而且能对设计进行完全覆盖验证。它不用波形或者激励而是直接采用硬件描述的方式，这样能更快得到结果和探测错误。